Microelectronics and Solid State Electronics

p-ISSN: 2324-643X    e-ISSN: 2324-6456

2014;  3(1A): 


Preface: Special Issue on Emerging Techniques for Nano-Scales CMOS Integrated Circuits Design

Kamal El-Sankary

Dalhousie University, Halifax, NS, B3H 4R2, Canada

Correspondence to: Kamal El-Sankary, Dalhousie University, Halifax, NS, B3H 4R2, Canada.

Copyright © 2014 Scientific & Academic Publishing. All Rights Reserved.

Despite Challenges, CMOS Technology is here to Stay. While several promising alternatives to replace silicon based CMOS technologies are actively developed; CMOS maturity, low manufacturing cost, high speed and low power consumption will extend its dominance for at least in the next ten to fifteen years. As the CMOS technology scales down to the nanometer level IC designers are facing several challenges including supply voltage reduction, excessive leakage current and statistical uncertainty with process variations and mismatch that all restrict the design of high performance digital, analog, mixed-signal, and RF circuits. Also the growing demand for more complex ultra-low power devices exacerbates these challenges and makes the operation reliability of integrated circuits despite of variations a hard to achieve goal.
This special issue of Microelectronics and Solid State Electronics includes the topics from analog integrated circuit synthesis flow, low-power RF circuits design and modeling, single-event transient testing for integrated circuits, and wireless network-on-chip to enable communication between processing cores.

Four innovative papers were selected after rigorous review process. The first paper, by T. Liao et al., describes a diverse analog integrated circuit synthesis flows to generate a quality-guaranteed tape-out CMOS designs. This paper puts emphasis on the impact of the Layout Dependent Effects (LDEs).In particular, two dominant LDEs, Well Proximity Effects (WPE) and Shallow Trench Isolation (STI) effects, are discussed along with experiments to illustrate the severity of the induced performance degradation on the next-generation analog synthesis methodologies and flows. The second paper, by H. Yu et al., presents a modified ultra-compact model which is numerically accurate for nano-scale bulk-driven low voltage nano-scale CMOS circuits. Also a guideline of quantitatively analysing nano-scale CMOS circuits is established. The distortion analysis of nano-scale gates and bulk-driven amplifiers is demonstrated as an example to show the importance of the nonlinear output conductance and the cross-terms

I would like to thank all the authors for their valuable contributions and all the reviewers for their time and efforts in helping to select the papers. I would like also to thank the Scientific & Academic Publishing supporting personnel for their expert help.
Finally, I hope that the readers of of Microelectronics and Solid State Electronics journal will enjoy reading the papers in this special issue and will find them useful in their future works on nano-scales CMOS integrated circuits design.