1. Introduction

The emergence of increasingly high speed, digital optical system, and optical processing demands an all optical divider to executing a set of optical arithmetic micro-operations. The performing of signal processing operations entirely within the optical domain would exploit the speed and parallelism inherent to optics[1, 2].

All-optical signal processing technologies are considered as a possible long-term route in the evolution of current telecommunication network and high-speed signal processing system[1]. In all-optical signal processing, all-optical binary divider is very important, which can have ultra-fast operating speed and eliminate the need of conversions between electronics and optics.

The all optical Divider can be constructed with an optical arithmetic unit depicted in ref.[2], and an optical parallel-shift register[3,5] based on cascaded optical flip-flop memories driven by common optical clock pluses. The optical flip-flop memory consists of two coupled polarization switches[4,5] sharing an all-optical DeMultiplexer (DMUX 1*2), Multiplexer, all optical ADC[6], optical ALU[2,10], optical multiplier[5], and all optical divider depicted in this paper can be used in the arithmetic operation to perform a fast central processing unit using optical hardware components. Ultra-compact optical flip-flops with a switching speed greater than 100 GHz were demonstrated[7]. This means that this concept has potential to be integrated and to perform at high speed.

2. Theoretical Description of Division

Binary division is simpler than decimal division because the quotient digits are either 0 or 1 and there is no need to estimate how many times the dividend or partial remainder fits into the divisor. When the division is implemented in a digital computer, it is convenient to change the process slightly. Instead of shifting the divisor to the right, the dividend, or partial remainder, is shifted to the left, thus leaving the two numbers in the required relative position[8].

Figure 1. The ASM flowchart of unsigned binary number

The unsigned binary division process is illustrated by the ASM flowchart depicted in figure 1. The divisor is stored in register (M), the dividend is stored in register (Q) and remainder is formed in register (A). The register (A) formed by the parallel-shift register according to the binary multiplier in refs.[5] and[8]. The contents of two register A and Q are shifted left and the most significant bit A₃ is tested after the subtraction between the contents of registers A and M. If A₃<0 the least significant of register Q is set to 1 and the subtraction occurs between the registers A and M, otherwise the least significant bit of register Q is reset to 0. The counter is decremented by one regardless of the value in A₃.

The counter is initially set to hold a binary number equal to the number of bits in the divisor. The counter is decremented after the formation of each partial division. When the content of the counter reaches to zero, the result of division is formed in the register (Q) and the remainder is formed in register (A) and the process stops at Z=0

3. The Optical Hardware Implementation for Binary Divider

Due to the lack of reliable optical logic devices, the signal processing technology used in current optical packet switched cross-connects and optical processing is based on a combination of electronic and optical technology[5]. The all-optical arithmetic operation such as multiplier and divider is carried out in electronics while the payload remains in the optical domain, where the over-all operation is implemented using all-optical hardware components. All optical divider have many potential applications in optical communication systems and optical computing which lead to construct an all-optical central processing unit.

This section describes an all-optical circuit that performs division of two binary optical words of 4 bits and could be used with all optical multiplier[5] for applications such as packet header processing and used in the construction of optical central processor unit.

The register configuration for the all optical binary divider is shown in Figure 2. The divisor is stored in register (M), the result of division is stored in register (Q) and the remainder is formed in register (A). The registers Q, and M are formed by an all optical register using optical D flip flops[5, 9] which designed before in ref.[5]. The register A is formed by an all optical parallel-shift register according to the all optical binary multiplier in ref.[5]. A binary all optical parallel adder[2, 10] is employed for subtracting the content of register (A) to the content of register (M).

Figure 2. All optical equipments configuration of optical divider

Figure 3. All optical Control Circuit for unsigned binary divider

3.1. The Optical Hardware of Divider Control Circuit

The control circuit of binary divider is considered as a sequential circuit, its control lines are depicted in the ASM chart shown in figure 1. The control lines T₀, T₁, T₂, and T₃ are chosen for the state boxes, the control lines Y₁, and Y₂ are chosen for the conditional boxes, finally there are three decision boxes S, A₃, and Z (Count=0). The state transition table of the control circuit according to the ASM flowchart is depicted in Table 1.

Table.1 The state transition table

The logic expressions for the control signals are obtained from state transition table as following:

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

The logic expressions from eq(1) to eq(8) are used for designing the overall control circuit of unsigned binary divider as shown in figure 3. The optical control circuit is controlling on the overall operation of all optical divider.

This optical control circuit consists of two all optical D flip-flops[5], all optical 2*4 Decoder[11], and set of optical AND, XOR and OR gates are formed by the hardlimiters[11, 12].

There are a set of semiconductor optical amplifier (SOA) are used for compensating the optical losses through optical fiber and optical couplers by adjusting the SOA currents injection from 241 mA to 283 mA for the different SOA’s.

The wavelengths of each flip-flop are 1550 nm for λ1 and 1552 nm for λ2. There is an external light input at wavelength of 1559 (λ3) is injected as clock pulse (ck) to optical flip flops.

3.2. Simulation Results of Optical Unsigned Binary Division

The numerical example is depicted in table 2 to clarify the proposed division process. The divisor is stored in register M, and the double length dividend is stored in register A and Q.

Table 2. Example of 2’s complement division

The input clock pulses have a wavelength of 1550 nm and duration of 0.45 microseconds and frequency of 1 MHz with optical peak power of 0.1 mW.

An all-optical optical parallel adder and all-optical arithmetic-logic unit based on cascaded optical all-optical full adders, optical Mux’s and all-optical logic gates was designed and numerically demonstrated with simulation at an operation of 10 MHz[2].

The parameters used in simulation for SOA are shown in table 3.

The overall optical fiber used is a single mode optical fiber with overall length equal to 15.6 m, where this long fibers effects on the time taken and the speed of division operation. So, the photonic integration technologies are used for increasing the overall speed of operation[15, 16].

Table 3. The parameters used in simulation Parameter Symbol Value Injection current of SOA I 241-283 mA Unsaturated single- pass amplifier gain Go 18-26 dB Line-width enhancement factor of SOA α 7.5 Gain recovery time τe 275 Ps Saturation energy of the SOA Esat 1.22

Figure 4 shows the simulated waveforms of the optical binary sequence control lines (T₀, T₁, T₂, T₃) for 16 clock pulses required after the start signal S to execute the division of the two number as example 0111(dividend) and 0011(divisor).

The contents of the two registers A and Q including the zero flag (Z) through the overall simulation process are shown in figure 5(a-b). All waveforms are scaled by arbitrary units and obtained using simulation computer aided design (CAD) of Beam propagation method.

Figure 4. Simulation result waveform of the control signals T0, T1, T2, T3

Figure 5. (a) Simulation results waveform of Register A. (b) Simulation results waveform of Register Q and Zero flag Z Divider

3.3. All Optical Signed Binary Divider

The proposed all optical divider can be used also for the division of signed numbers except the setting of Qo=1 step is eliminated from the overall process of flow chart as shown in figure 6[14].

Figure 6. The ASM flowchart for signed binary number

4. Conclusions

An all-optical binary divider and its all-optical control circuit of unsigned binary division based on all optical parallel shift register at an operation of 10MHz to100 MHz, all-optical arithmetic unit based on the design of ref.[10] are designed and proven using the numerically simulated (Beam propagation method V.5) at an operation of 1MHz to 10 MHz for the overall division process.

All-optical system computation eliminates the conversion from optical to electrical and vice versa. Accordingly, the latency is smaller than that using electrical digital computation. The time taken by each all-optical digital device is reduced to sub nanoseconds by building integrated Bragg gratings and optical fibers on SOI ridge waveguides[13, 7], where the optical integrated circuit processing is going to fabricate the fiber Bragg grating, SOA, TOAD elements, optical amplifiers and all optical digital circuits using the semiconductor devices[15, 16]. The operation speed may increase to perform a fast optical central processing unit by using the photonic integration, which would decrease the dimensions of the building blocks.

Acknowledgments

The author would like to express his great thanks for Prof. Elsayed M. Saad and the late prof. M. K. Ahmed.