1. Introduction

Power consumption has become one of the most critical issues during the design of battery operated portable systems. Design methodologies and related tools enabling the control on the power budget during the different phases of the design flow are mandatory. The main components of such portable systems are processing unit, the memory controller, memory chips. It is anticipated that the embedded memory will account for 95% of the chip area in the complex systems[1] and the communication channels which provide data transfer between the CPU and the memory. During thecommunication of these components bus power consumption is proportional to the switching activity. The switching activity of the buses is often responsible for a substantial fraction of the total power dissipation for large VLSI modules. As the compelxity of the system increase the number of data buses and address buses incresses. The large and long interconnects dissipates as dynamic energy dissipation for charging and discharging of internal node capacitances and inter-wire capacitances.

Testing of the memory sections is a tedious job because in memory testing the bunch of the data is written and read again and again for all the memory locations at very high speed. During memory testing power dissipation increase drastically due to excessive switching in test patterns. Therefore, it needs low power encoding techniques for communication between devices or on chip communication. To access a Memory Under Test (MUT) address buses are required to access memory locations and data buses for sending test patterns. Thus, the minimization of the transitions can provide significant savings on the overall power budget. To accomplish this job there is a need of very fast processors which are connected in parallel to provide the very high testing rate. SCAN based design are mostly preferred for memory testing[1]. During writing and scanning first, write 0s to the memory in ascending order of address. Second, read the memory (expect to read a 0) and then write a 1 in ascending order of address and third is to read and write a 0 in descending order of address. Finally Fourth, read the memory (expect to read a 0). However testing time of a scan system is proportional to both the number of test patterns and the number of flip-flops in the scan chain(s). In a modern VLSI circuit, the numbers of internal flip-flops are in the range of thousands or even higher, therefore, to reduce test application time and large amount power consumption become an important issue, that needs to be optimized along with speed and area. Power consumption is directly related to the number of times flip-flops toggle their states i.e. toggling rate, so intention is given to arrange the test vectors in such a manner that minimum toggling occur in a Memory Under Test (MUT). Thus, the minimization of the transitions can provide significant savings on the overall power budget. The relation between power and switching rate is related according to equation 1.

(1)

Where represents biasing voltage, C(g) is the output capacitance of the nodes and toggle(g) is switching of the gates ‘g’.

VLSI circuits with large power dissipation require expensive packaging to ensure appropriate heat dissipation. Excessive power dissipation results the overheating of the MUT, and probability of damage are increased at testing time. Thus most research efforts have focused on reducing the dynamic power consumption during memory writes and read cycle by reducing the transitions.

The rest of the paper is organized as follows: In the next section, we reviewed the related work on the bus encoding schemes for low power. In section 3, the Bit Invert, Bit invert signaling, ABIT and Proposed Scheme for power reduction during the data are explained. Then the encoder and decoder are designed for these schemes and implemented on FPGA. In section 4, the address encoding schemes are discussed and implemented for the memory addressing. In section 5, we have compared these schemes on the basis of power, Area & energy efficiency for the reference data. In the last section conclusion is drawn.

2. Related Work

Luca benini et. al.[3] presents the low power address bus encoding technique to sort out the problem of power dissipation for intellectual proprietary core processor. Here reduction in bus activity is achieved with this technique. Yazdan Aghaghiri et. al.[18][4] in this T0 and Offset- XOR encoding techniques are discussed and irredundant bus encoding for low power is presented and its benefit over the other techniques are presented, and it is shown that this method of irredundant saves 83% of power. Prabhat K. Saraswat et. al.[13] uses gray code and T0 code for memory address bus encoding. Bits encoded n such way the bit switching activity is reduced on the address busses. The sequences of addresses are generated of specified sequentialty and evaluated the performance of both codec’s.

Sathish et.al[10] suggested a Efficient Switching Activity Reduction Technique for Fault Tolerant Data Bus for Deep-submicron (DSM) systems. The proposed encoding technique reduces the switching activity by 18% to 22.5%. Its efficiency is 8% to 15% more compare to others encoding techniques. Youngsoo et.al[8] presents a partial bus-invert coding scheme for power optimization of system level bus. In the proposed scheme, they select the sub-group of bus lines for bus encoding to reduce the total number of bus transitions. It reduces the total bus transitions by 62.6% on the average, compared to that of the unencoded patterns.

Ghoneima et. al[22] proposed a low power on chip the serial-link bus (SLB) architecture which reduces the number of bus lines of the conventional parallel-line bus (PLB) architecture by multiplexing each m-bit onto a single line. In another paper , Sinha et.al[23] authors have proposed a bus encoding technique using Forbidden Transition Free Algorithm for Cross-Talk Reduction for On-chip VLSI Interconnect.

3. Data Bus Encoding Technique for Memory Testing

Bus-Invert Method: This technique is based on Hamming Distance between the consecutive test vectors. Test patterns generated by the Automatic Test Pattern Generation (ATPG) are encoded according to their hamming distance before it sends to Circuit Under Test (CUT). The encoding depends on the Hamming distance between the value of the encoded bus lines at time t-1 (also counting the redundant line at time t-1) and the value of the bus lines at time t.

The bus-invert encoding method can be expressed by the following equations[5]]2]:

Where B (t) is the value of the encoded bus lines at time t,

INV (t) is the additional bus line,

b (t) is the address value at time t,

is the Hamming distance, and N is the bus width of b (t).

The corresponding decoding scheme is simply defined as:

Major drawback of this approach are related to the required redundant bus line and the overhead due to the logic to implement the voter to decide whether the Hamming distance exceeds N / 2.

Bus Invert Transition Signaling: With transition signaling a logical 1 is represented by a transition (from HI to LO or LO to HI) while a 0 is represented by the lack of such a transition. Transition signaling will not reduce switching activity by itself[5]. If transition signaling is used and at the same time we reduce the number of 1’s in the code words we can directly reduce the switching activity on the bus.

Transition signaling combined with bus-invert (BI) coding, is called BITS coding. BITS reduce the number of logical 1s transmitted over the bus,[4] that are responsible for all the high-to-low and low-to high transitions, while the logical 0s are represented by the lack of transitions.

In BITS encoding, if the number of ones in the incoming data is larger than half the bus width, then each bit of incoming data is inverted and INV is set to one (1) and then transition-encoded. Otherwise, each bit of incoming data is transition-encoded without alteration. More precisely, for a pattern at time, (Xi), its BI-encoded version is given by:

where | denotes a concatenate operation, I denote the value at the invert line, w (Xi) denotes the number of 1’s in Xi, and n denotes the bus width.

Then, the BITS-encoded version of Xi is given by

where TS(x; y) denotes a transition encoding of x with respect to y.

The decoding process can be carried out by

where

Note that both TS(x; y) and its inverse TS-1 (x;y) can be implemented by XORing x and y

In Approximate BITS encoding[8] technique, numbers of transitions are reduced as compared to the simple and BI (bit inverse) method. Due to which the total power of the circuit is reduced. Its application to real circuit design is limited by the extra bus line, which calls for change in pin out and interface specification of the original chip. As the main overhead comes from a majority vote, that decides whether to encode 1 or 0 as having a transition, we eliminate the voter by moving to another technique which is ABITS. In ABITS method, the guess relies on the MSB of each input bus. This means that MSB takes over the function of invert line thus eliminating the need for an extra bus line. In ABITS method, the output function Y is the XORing or XNORing depending upon the MSB of input data.

Although ABITS encoding obtains less transition reduction due to incorrect guess, the overall power consumption (including the power consumed by the encoder itself) is fairly comparable to that of BITS encoding because the ABITS encoder consumes less power than BITS encoder.

Proposed Technique for Encoding: The proposed technique has an edge over other existing techniques that it has no redundant line. Due to which an extra expensive pin is saved. This technique works for all data streams except for the stream containing all 1’s.

Encoder

In this technique the encoder is used for encoding the transitions. It takes 8-bit input word as input bit stream and functions as:

.

Decoder

The decoder is used for decoding the output generated from the encoder. It takes transmitted word as input bit stream and then computes the original input word X(n). It functions as:

.

Encoding function should minimize the average number of ones at its output while the encoded value Y(n) can still be uniquely decoded by D.

4. Address Bus Encoding Technique for Memory Testing

In memory testing read /writes operations are performed according to the algorithms such as March. One address generator is also required for the addressing the memory locations. In this switching also takes place, causes the power dissipation. This switching can be reducing with various address encoding techniques. To encode the address bus for test with least switching activity various methods like gray encoding and T0-C encoding. By utilizing the sequential addressing instead of using random addressing reduces the power dissipation in the address line by reducing the toggling count. But after some clock cycles even the in the sequential addressing the toggling count is increased by the unity value. Due to that here we concentrate on T0, gray code base addressing and irredundant bus encoding. In gray encoding the toggling count is fixed to the unit value, which saves the power dissipation. To even reduce the toggling value beyond the unit value the technique preferred is the T0-C encoding. To save more power, instead of using gray coding T0-C encoding is used. In case of simple T0 encoding the process of sending address bit is shown in table1, below:

Table 1. T0 encoding b(t) B(t) 39 39 40 39 41 39 39 39

As when we reach the last row of the table, no valid code word can be generated for source word 39. If we use 39 as the code word, the receiver (decoder) cannot determine whether the source word was 39 (backward jump) or 42 (next sequential address). So the error appears when the data on the bus is equal to the branch target itself. That is why spatial redundancy was originally introduced into the T0 code.

In T0-C when such a case occurs, we set the code word to b(t-1) + S. The reason is that this is the only pattern that the receiver should not expect from the sender. Notice that when the receiver sees a value of b(t-1) + S, it knows that the sequential addressing has been stopped because the bus value has changed. On the other hand, when it computes the new jump address, it recognizes that this jump address is the same as the next sequential address. Therefore, if in fact a special case were not encountered, there would be no need for the sender to unfreeze the bus value. This special case is, of course, when the target of the backward jump is the same as the current value on the bus. The decoder is aware of this, and ambiguity is resolved. T0-C encoder works as follows:

if {b(t) == b(t-1) + S}

B(t) = B(t-1)

else if {B(t-1) != b(t)}

B(t) = b(t)

else

B(t) = b(t-1) + S

On the receiver side, when the b(t-1) + S value is received, the previous value on the bus is regarded as the branch target. For the previous example we will have:

Table 2. T0 –c encoding b(t) B(t) 39 39 40 39 41 39 39 42 40 42

Gray code address generator

The term Gray code or reflected binary code is referred to a binary sequence in which only a single bit changes value when transition between adjacent states occurs. A Gray code can be generated by changing the least significant bit that results in a new state. The next sequence creates a mirror image of the existing gray code below the original value. The binary values can be converted to gray codes by XORing the bits. Let us consider a 4-bit binary value B and 4-bit gray output G. B can be converted to G as:

The gray code counters are popular in digital system for a variety of applications, such as representing the state variables in state machines or acting as pointers in First-In First-Out (FIFO) memories, and also can be used as address counters. This is because in gray code counters only one output bit is ever toggling at a time in as opposed to multiple bits in a binary counter. These counters count the values in gray codes only. The advantage of Gray code counters over others is that they consume only half the power of an equivalent binary counter and correspondingly less noise.

5. Bus Power Model for Encoding Scheme

Let us assume, power P watt will be dissipate when switching takes place in any of the bus line. System bus switching can be calculate for n bus lines then the power dissipation is n * P watt and so to calculate the switching activity[15]. The power dissipation on the bus is calculated by applying all the encoding techniques on the reference data as taken in Table 5.

Power dissipation is given by:

(2)

α = Switching activity

V_dd =Supply voltage

f = Frequency

C_L= Load Capacitance

The encoding efficiency E is an important parameter for the comparison of various encoding techniques as given by equation[Reference], which is technology independent and gives only reduction in switching activity.

(3)

in order to determine the Power savings in overall power consumption, the self dissipation of encoder and decoder circuits has to be considered as well. The power savings are given by equation:

(4)

_uncoded = power consumed for un-coded data streams

P_coded = power consumed for coded data streams

P_encoder = power consumed by the Encoder

P_decoder = power consumed by the Encoder

The percentage of bus power saved due to coding is given by the energy efficiency EP in equation

(5)

Energy E_p >0 then power is saved. For E_P<0 the total power consumption is increased by this encoding technique. To save Power, the Encoder and decoder has to be small and the power consumption of the encoded bus has to be sufficiently lower than the original un-coded bus.

6. Experimental Results

Table 3. Power calculation for data encoding scheme

Table 4. Power calculation for Address encoding schemes

In this section, we present the details of our experimentation setup and discussion on the results obtained with various encoding techniques:

The I/O voltage was assumed to be 3.3v, Frequency of 10 MHz, and switching activity is estimated for the reference data taken in table no 6. The encoders and decoders are designed for the encoding schemes in HDL with the NC launch cadence tool. The power consumption and cell area is calculated for these schemes are shown in table 3. The number of transitions is calculated with transition counter for the reference data of table.

As the results shows that proposed scheme number of transitions are reduced by 33% from un-coded data and 29.6% power is saved whereas in Bit Inverse and Bit inverse transition signaling techniques reduces power only 15.6 and 20.4 respectively and also uses an extra bit line for inverse logic indication. ABIT save this extra line but power saving is less than these schemes. The proposed scheme saves more power without the extra line overhead.

In memory testing read /writes operations are perform according to the algorithms such as March. One address generator is also required for addressing the memory locations. In this switching is also take place, which causes the power dissipation. This switching can be reduced with various address encoding techniques. The power consumption and cell area is calculated for address encoding schemes for reference address locations are shown in table 4.

Table 5. Reference address locations & Hamming Distance Calculation of Various encoding scheme

Table 6. Reference Test Patterns & Hamming Distance Calculation of Various encoding scheme

7. Conclusions

The low power bus encoding techniques play an important role in reducing the switching activity during the on chip communication. Testing of the memory is very important because 90% of the chip area is occupied by memory. During memory testing many read /writes operations needs to be test according to the March algorithms) to achieve 100% fault coverage. In this paper we have implemented bus encoding schemes for memory BIST. The encoding schemes are applied to the data bus and address bus by taking the reference data. The power consumption of various encoding schemes is shown in figure 1. It is observed from the results of proposed scheme for data encoding is 33% less switching activity occurs and about 30% of average power is saved. In case of address encoding that 71.2 % less switching activity occurs and about 74.8 % of average power is saved is shown in figure 2

Figure 1. Power consumption of Various Data Encoding Schemes

Figure 2. Power consumption of Various Address Encoding Schemes