Electrical and Electronic Engineering

p-ISSN: 2162-9455    e-ISSN: 2162-8459

2018;  8(2): 29-36



FPGA-Based Analog-to-Digital Conversion via Optimal Duty-Cycle Modulation

Sonfack Gisèle Béatrice1, Mbihi Jean2

1Electronics Department, Faculty of Science, University of Dschang, Dschang, Cameroon

2Laboratory of Computer Science Engineering and Automation, ENSET, University of Douala, Douala, Cameroon

Correspondence to: Mbihi Jean, Laboratory of Computer Science Engineering and Automation, ENSET, University of Douala, Douala, Cameroon.


Copyright © 2018 The Author(s). Published by Scientific & Academic Publishing.

This work is licensed under the Creative Commons Attribution International License (CC BY).


In this paper, a FPGA-based Analog-To-Digital conversion (ADC) architecture via ODCM (optimal duty-cycle modulation), is designed and implemented using software and hardware co-simulation platforms. The software platform consists of Simulink/Xilinx-based system generator blocks in which the ODCM-ADC is implemented, and of Xilinx ISE programing tool for FPGA chips. The hardware platform consists of Zynq 7000 FPGA Kit (25 MHz sampling clock), equipped with an embedded second order FPGA-based digital IIR (infinite impulse response) decimation filter, and with a PC-based JTAG communication cable/connectors. The co-simulation systems, are built and successfully tested for 3 KHz modulating bandwidth. The resulting normalized characteristics are given by: SNR = 49.55 dB, SFDR = 41,19 dB and Noise Floor Range =140 dB. These performance levels obtained under virtual and hardware co-simulation conditions, show a relevant challenge of ODCM-ADC, compared to most types of oversampling ADC techniques. As a merit, the proposed FPGA-based ADC technique is a novel and relevant ADC architecture for embedded instrumentation systems.

Keywords: Analog-to-digital conversion, Optimal duty-cycle modulation, IIR decimation filter, FPGA, JTAG communication, Virtual and hardware co-simulation, Embedded instrumentation systems

Cite this paper: Sonfack Gisèle Béatrice, Mbihi Jean, FPGA-Based Analog-to-Digital Conversion via Optimal Duty-Cycle Modulation, Electrical and Electronic Engineering, Vol. 8 No. 2, 2018, pp. 29-36. doi: 10.5923/j.eee.20180802.01.

1. Introduction

Most artificial and natural signals to be captured for digital processing purposes are analog quantities and consists of a finite frequency spectrum. As an implication, the ADCs (analog-to-digital converters) with a suitable sampling frequency according to Nyquis’s theorem, are widely used in modern instrumentation systems. Although the ADC concept is simple ideally, building an optimal realistic ADC device has been overtime and remains, an intricate and active problem in electronic instrumentation engineering practice. This is due mainly to the fact that each family of ADC devices is designed and implemented for a target application areas, with intrinsic technical and qualitative requirements. As an example, the oversampling ADC architectures, are suitable for instrumentations problems involving servomechanisms, temperature regulation, lighting processes and audio systems [1, 2].
The most popular candidate within this class of oversampling ADC systems is the sigma-delta ADC architecture. Surprisingly, in 2012, a novel oversampling ADC architecture founded on the DCM (duty-cycle modulation) principle, has been studied and well tested with satisfactory results in [4, 5]. However, the following technological problems were outlined: Use of a PC (personal computer) as the DSP (digital-signal-processing) core for real-time oversampling high frequency on/off modulating signals, unreliability of the PC-based clock required for the oversampling process, and implementation of the digital decimation process as a Visual Basic application program. Given these technological problems, it is worth noting that the limitations related to the DCM-ADC architecture, relies on the PC-based environment used for digital signal processing tasks. Indeed, many studies conducted in most recent papers indicate that, the DCM principle provides numerous relevant technical properties and high quality [6, 7], while numerous intricate weaknesses are hidden behind the popular sigma-delta ADC architecture, e.g., higher structural complexity, higher order n-bit decimation filter for reaching a good accuracy, lack of exact analytical models for rigorous design and analysis purposes, and more. It is worth noting also that, although the DCM principle has also been used satisfactory beyond ADC application areas, e.g., DAC (digital-to-analog converters) [8-11], signal transmission [12, 13], and power electronics [14-16], little attention has been devoted to the ODCM problem studied in [17], under Matlab/Simulink framework.
The aim of this paper is to develop a FPGA-Based framework for software-hardware co-simulation processes of an ODCM-ADC architecture (virtually modelled in [17]). The co-simulation results obtained at this development research will be very relevant, for a realistic evaluation of technical requirements when using FPGA-based ODCM-ADC technology in embedded electronic instrumentation systems. The remaining content of the paper is organized in several additional sections. Section 2 deals with a brief recall on the ODCM-ADC architecture. In section 3, the FPGA-Based ODCM-in ADC co-simulation processes are presented. Then, the FPGA-Based ODCM-ADC design is conducted in section 4 from Simulink/Xilinx block sets and also using Xilinx ISE programming tool for FPGA chips. Furthermore, in Section 5, the prototyping FPGA-based ODCM-ADC converter is well tested from software and hardware co-simulation processes, and a sample of relevant results obtained are presented. Finally, the paper is concluded in Section 6.

2. Recall of ODCM-ADC Architecture

A similar schematic diagram of an ODCM-ADC designed in [1], is recalled in Fig. 1. It consists of two main parts, connected in tandem, i.e., an upstream optimal DCM circuit (see Fig. 1(a)) with modulating input x and DCM output xm(t), and a downstream optimal digital IIR (Infinite Impulse Response) filter (see in Fig. 1(b)). The optimal DCM circuit is designed according to a set of nonlinear parametric optimization problems with constraints, whereas the optimal IIR filter is synthesized according to the weighted least pth norm specifications.
Figure 1. ODCM-ADC architecture
The optimal parameters of the prototyping ODCM-based ADC system considered in this section are: fs = 25 MHz (sampling period or Ts = 1/fs = 40 ns equivalently), fs = 3 KHz (Modulating bandwidth), fm(0)=172 KHz (basic oversampling DCM frequency), E=9 volts (power supply), α* = 0.012366816265686 where α* = R1/(R1+R2) and RC=0.000115510618677 s. It is worth recalling from [17] that the DCM circuit shown in Fig. 1 is modelled by equation (1), which is quite easy to be implemented in Matlab/Simulink framework.
In addition the z-transfer function of the optimal second order digital IIR decimation filter is given by (2).

3. FPGA-Based ODCM-ADC Design

The FPGA-Based ODCM-ADC design is conducted under Simulink workspace, according to the schematic diagram presented in Fig. 2. The upstream subsystem shown in Fig. 2(a) is a Simulink-based model of the DCM circuit given by (1), with analog modulating input Xs ≡ x as in Fig. 1(a), and with a sampled modulation output xm.
Figure 2. FPGA-Based ODCM-ADC design architecture
Then, the downstream subsystem presented in Fig. 2(b) is modelled as a digital IIR filter given by (2), which is implemented using visual building resources and configuration panels available in Xilinx System generator framework. The IIR filter is implemented according to the direct form approach. The implemented only required 5 multipliers, 5 registers and an added tree, although the full resolution is maintained across the multipliers and the tree. In addition, the data width cannot grow indefinitely, and thus a quantization block is placed at the output of the adder to reduce the width of the data.
At this step, it is worth noting that the whole schematic diagrams presented in Fig 2, is tested over the modulating bandwidth followed by the creation and the configuration of an additional hwcosim block for further hardware co-simulation requirements. In addition, the DSP code for the target FPGA is generated as an input module for Xilinx ISE framework. As an implication the related high level RTL diagram shown in Fig. 3, is organized into 9 digital processing modules.
Figure 3. RTL diagram of the digital IIR decimation filter
Furthermore, a sample of the corresponding waveforms shown in Fig. 4 is created and well tested also, for the sake of better inspection and validation. The last step of the FPGA-based design process relies on the production of the embedded FPGA file to be executed during software and hardware co-simulation time.
Figure 4. Waveforms of the FPGA-Based ODCM-ADC generated under Xilinx ISE
Furthermore, a sample of the corresponding waveforms shown in Fig. 4 is created and well tested also, for the sake of better inspection and validation. The last step of the FPGA-based design process relies on the production of the embedded FPGA file to be executed during software-hardware co-simulation time. From Fig. 4, the following relevant findings could be pointed out:
1) The bits streams of signals involved, are displayed only over a few sampling period for the sake of clarity. The effective simulation time is sufficiently large in order to cover a few periods of the modulating signal.
2) The oversampling period of the clock signal named (clk) is T = 950 ns – 940 ns = 10 ns. The waveforms of associated RTL signals are displayed from 931 to 950 ns (time interval).
3) The discrete values of the digital IIR filter response named “filter_out” change over time.

4. Co-Simulation of the FPGA-Based ODCM ADC

The co-simulation is a powerful modern technique, which is widely used nowadays for rapid testing and evaluating at design time, the predicted and realistic performance of a DSP-based system [18, 19]. Indeed, the co-simulation processes require a PC-based virtual simulation application for DSP (digital signal processing), and a target DSP board equipped with an embedded version of the application code to be simultaneously executed with the virtual application. Both PC and DSP board are connected via an appropriate communication cable/connectors (USB, Ethernet or JTAG). Thus, in a hardware co-simulation context, digital signals involved in a DSP/FPGA chip, are uploaded automatically to the PC-based virtual platform for real-time monitoring.
During a co-simulation session, the virtual simulator and hardware DSP are simultaneously launched and driven under the same operating conditions (input and parameters), while the real-time behavior of the hardware DSP is brought to the virtual simulation environment for the sake of rapid design, performance visualization and evaluation. The co-simulation environment created in this research work for rapid computing and evaluating both predicted and experimental characteristics of the prototyping FPGA-based ODCM-ADC, is presented in Fig. 5.
Figure 5. Hardware Co-Simulation environment
Indeed, the co-simulation environment is a hybrid framework consisting of virtual and hardware subsystems. It is worth recalling that the virtual simulation subsystem is a Simulink/Xilinx-based simulator for the ODCM-ADC. Alternatively, the target hardware processing subsystem is a FPGA development Kit, with executable code of the IIR filter, uploaded at design time into the embedded FPGA memory. It is connected to the PC-based Simulink virtual environment via a JTAG (Joint Test Action) cable, and simultaneously run with the virtual simulation subsystem.

5. Co-Simulation Results

A number of relevant results have been obtained when testing the characteristics of the prototyping FPGA-Based ODCM-ADC in the co-simulation framework. These relevant results are summarized in Fig. 6. Fig. 6(a) shows in the time domain the graphs of 3 signals involved (modu- lating, hwCosim output and Gateway output). It is a challenge to observe in Fig. 6(b) that, even under widely zoomed vision scale, the gap between the graphs of modulating and hwCosim output signals remains negligible. In addition, the values of SNR, SFDR and NOISE FLOOR range computed from Fig. 6(c) and Fig.(d) are 49.55 dB, 41.19 dB and 140 dB respectively.
Figure 6. Summary of a sample of Co-simulation results obtained
In addition, in Fig. 7, it is worth noting that, the proportion of FPGA resources used for the real-time implementing of the ODCM-ADC architecture is highly low. It is also relevant to evaluate the effective resolution m(x) of the ODCM-ADC architecture according to the expression (3) as outlined in [8] and [10].
In (4), the parameters R, C, α = R1/(R1+R2) and E, are those of the DCM circuit in Fig. 1(a), whereas fech and fm(x) stand for the sampling frequency and the DCM frequency respectively, given a modulating input x. It is obvious that (3) is minimum if fm(x) is maximum. Then, following convexity Theorems (see [17] for statement and demonstration), (4) is maximal if x = 0, in which case fm(0) is given by:
In this case, the minimum value of (3) is given by (6):
As a relevant implication arising from (6), for a fixed modulating bandwidth, an increase in the oversampling frequency fech is a simple means to increase the ENOB (effective number of bits) of the proposed FPGA-based ODCM-ADC architecture.
Figure 7. Proportion of FPGA resources used for the implementation of ODCM-ADC/
In this paper, the optimal parameters used and recalled in section II are given as follows: fech = 25 MHz, RC = τ = 0.000115510618677 s, α* = 0.012366816265686, then fm(0) =172 KHz and the resulting ENOB (effective number of bits) is 7.1554 bits. Since the advances on today’s FPGA technology lays beyond 500 MHz [20] and even 1.5 GHz of clock frequency [21], the application areas of the FPGA-based ODCM-ADC architecture might rapidly grow over time. However, compared to the technical behavior of most popular candidates operating today within the class of oversampling ADC architectures [22-26], these levels of performance provided by the FPGA-based ODCM-ADC, might be a great challenge under the same operating conditions (modulating bandwidth, sampling frequency, single stage DCM interface, second-order digital decimation filter, no external modulation clock, and more).
As a relevant finding, the proposed FPGA-based ODCM-ADC is relevant for embedded instrumentation systems.

6. Conclusions

This paper presents the design and FPGA-based implementation, as well as the hardware co-simulation of the proposed ODCM-Based ADC. The design and co-simulation have been sussesfuly implemented on a target Xilinx ZYNQ 7000 FPGA memory kit. It is worth noting that the ODCM-based ADC owes its low implementation cost and high quality (stability, accuracy and robustness) to both the harware simplicity and the topological relevance (negative and positive feedback loop) of its interfacing DCM circuit. As a relevant mayor finding, the new FPGA-based ODCM-ADC presented in this paper, might be used as a new potential architectural solution for embedded instrumentation systems.


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