1. Introduction

The wireless communication market is undergoing a major expansion with the deployment of new technologies and standards opening the prospect of significant impacts in many application areas (security, health, automobile, telecommunications, robotics…). The emerging wireless technologies require architectures with reduced complexity, cost and power consumption; however, they require more accuracy and performance of specific circuits.

This evolution pushes designers both to find new architectures of circuits and systems which can offer high performance, low-cost and low power consumption, and also to use new CAD (Computer-Assisted Design)methodologies able to model the mixed-mode behavior (analog / digital) of these systems. Currently, the hardware description language is widely applied in the design of mixed-signal circuits. Indeed, the VHDL-AMS standard allows the implementation of the top-down hierarchical approach for analog and mixed systems[1,2,3]. Therefore, it can be used for behavioral modeling and design of phase locked loop (PLL), which is a key element for any wireless communication system. Standard PLL frequency synthesizers with integer–N and channel spacing. The fractional-N technique offers wide bandwidth with narrow channel spacing and alleviates phase locked loop (PLL) design constraints for phase noise. The ∑∆ fractional-N PLL[4, 5] is attractive for frequency synthesis or direct modulation. This architecture can still meet requirements such as low-power consumption and simple topology, and is suitable for high-level integration.

The design of fractional-N PLL synthesizers, however, requires an iterative design process due to the large set of system parameters that must be optimized to achieve the desired phase noise, settling time, and fractional spur rejection. In addition, a ∑∆ modulator used toinstantaneously alter the feedback division modulus introduces excessive phase noise and fractional spurs. A behavioral level simulator is required to reduce the design runtime as well as assess the phase noise contribution and fractional spur rejection of the ∑∆ modulator before the physical design phase. In the literature many papers have studied the implementation of the behavioral models of classical PLL systems and ∑∆ synthesizers[6, 7, 8].

However, there are few works that show the full analysis and design of ∑∆ synthesizers using behavioral modeling. In this paper, a ∑∆ fractional-N PLL is modeled using VHDL-AMS and synthesized for a wireless application. For this study, many HDL models have been studied and tested for different PLL blocks. A comparison with transistor-level simulations validates the proposed models.

This paper is outlined as follows. In section 2, we detail the proposed hierarchical design flow. In section 3, we describe how to determine the modulator parameters. In section 4, we detail the high level description of the studied system. In sections 5, we present a second optimization step to improve the lock time with experimental designs. In session 5, we detail the modulator characterization. Section 6 draws a conclusion.

2. The Proposed Hierarchical Design Flow

The common method for the PLL loop filter design starts by deciding a frequency range, a channel spacing and N counter value. Then, we choose arbitrary the values for filter parameters, calculate filter components and then analyze. If the loop filter does not meet lock time and spurious requirements, then we adjust parameter values and re-optimize. The disadvantage of this common method is that it is an iterative process, very time consuming and based on trial and error. Furthermore, it does not always achieve the optimal solution.

Dean Benerjee et all propose in[9] a new approach which reduces the number of iterations to do. With this approach, we give the frequency range and the channel spacing. The N counter value is the consequence of these two parameters. We then come up with system requirements especially lock time and spur level. Once we have an idea of these requirements, we select the charge gain, the Voltage Controlled Oscillator (VCO) gain and the VCO input capacitance.

An intelligent algorithm helps to converge to the best solution and then calculates the filter components to meet the lock time and the spur level requirements. The proposed new approach was applied to develop “Easy PLL” software. Easy PLL basically allows to set system requirements, determine loop filter’s components and then do simulations to examine various types of waveforms.

In[10], Antonio Calaci et al propose a systematic analysis and optimization of analog and mixed signal circuits balancing accuracy and design time. In fact, since both systematic sizing approaches and statistical analysis require many simulations, Antonio Calaci applies a hierarchical approach with different levels of simulation and accuracy from system to transistor level to balance the tradeoff between time and accuracy. All sizing and optimization steps are driven by WiCkeD[11], an EDA environment independent tool for circuit analysis and sizing. WeiCkeD does statistical optimization with a unique deterministic worst-case distance algorithm.

M. Henderson Perrott uses VppSim software environment to compute the PLL parameters[12]. VppSim provides a software framework that supports Verilog and C++ co-simulation within the Cadence environment. VppSim therefore provides a top-down design methodology in which designers start at the highest level with CppSim modules, and then gradually build more granular models using Verilog and Spectre. Designers can also benefit from the ability to convert CppSim systems created within Cadence into Matlab or Simulink functions.

In our case, we developed a simulation platform to simulate ∑∆ fractional-N PLLs acting as a direct modulator. The hierarchical design flow we use is detailed in Figure 1. First, the phase noise specification is fixed, and then the PLL bandwidth is calculated. With CppSim, we compute the PLL parameters. An initial solution is obtained which respects the phase noise constraints. However, the PLL is not necessary a fast locking one. For this reason, we developed an optimization interface based on a genetic algorithm to converge to a faster PLL. At this step, only a functional PLL model is employed. In a second step, fractional-N PLL is described in VHDL-AMS and simulated in Simplorer 7.0 software. The PLL lock time and the spur rejection are simulated with the optimized solution. If the required specifications are not reached, a second optimization based on experimental designs is done.

Compared to previous works, the hierarchical design flow we propose presents the following advantages: first phase noise specifications are respected when calculating the different PLL parameters. Second, we show that it is possible to improve the solution obtained with CppSim when adding an optimization interface based on a genetic algorithm. Third, the second optimization based on experimental designs helps to converge to a better solution after doing few simulations with a multi-abstraction VHDL-AMS description of the fractional-N PLL.

Figure 1. The proposed hierarchical design flow

3. Determination of the Modulator Parameters

Figure 2 shows the block diagram of the studied modulator[13-14]. It is a mixed system composed of both analogue and digital parts. It is based on a fractional-N frequency synthesizer directly modulated at high data rate with a ∑Δ modulator. This technique achieves good noise performance. In fact, it allows digital phase/frequency modulation to be achieved at high data rates without mixers or D/A converters in the modulation path.

The synthesizer is implemented as a PLL. To achieve good noise performance with a simple design, the PLL bandwidth is set to a low value relative to the data bandwidth. To illustrate our design approach, the described modulator is used to build a 1.92 GHz to 1.98 GHz transmitter respecting the Universal Mobile Telecommunications System (UMTS) standard[14].

Our target consists in reducing the PLL lockup time, maintaining reduced spur level and phase noise and having a capture range covering the UMTS frequency band.

Figure 2. Block diagram of the modulator

3.1. Pll Parameters Determination with Cppsim

Table 1 resumes the main parameters of the modulator (I_cp, R, C₁, C₂ and K_vco). With the help of CppSim system simulator, we start our design flow by extracting initial values of these parameters. In this case, we compute the bandwidth of the PLL, and CppSim extracts the open loop parameters as shown on Figure 3.

The PLL bandwidth f₀ is calculated in order to achieve a phase noise respecting the UMTS specification (less then -118 dBc/Hz@1MHz). The phase noise performance can be separated into two components: intrinsic noise and quantization noise. Intrinsic noise is due to circuit elements present in any PLL, including reference input jitter, reference feed through, charge-pump noise, and VCO phase noise. Quantization noise, which is caused by dithering, is particular to fractional-N synthesizers. The power spectral density (PSD) of the quantization noise appearing at the output of the synthesizer (after being filtered by the PLL dynamics) can be expressed by the following noise model[13]:

(1)

T is the input reference period, f₀ is the PLL bandwidth, m is the PLL order and n is the Sigma Delta modulator order. When supposing m=n, we can deduce the expression of the PLL bandwidth:

(2)

For T=1/26 MHz, n=1, m=2 and = -118 dBc/Hz, we obtain f₀ = 84 kHz.

Table 1 shows the obtained values for the different parameters of the modulator.

Table 1. Parameters of the modulator Charge Pump current Icp = 1.5 µA Loop Filter components R = 416 kΩ, C1= 3 pF, C2= 30 pF VCO characteristics Kvco = 30 MHz/V, f0=1950 MHz Frequency reference 26 MHz Frequency Divider ratio N= 73.84 to 76.15

Figure 3. PLL design interface

Figure 4 shows the simulated response of the loop filter (simulation in Sue2[12]). After a transient regime, the PLL is locked after 18.41µs. The simulated spur level is equal to -109 dBm.

Figure 4. Loop filter response with Sue2

As detailed in Table 2 the UMTS specifications are not all reached. In fact, the PLL capture range is lower than the UMTS frequency hand; the maximum data rate is about 1.3 Mbps, lower than 2 Mbps and the spur level is still high. The modulator parameters are consequently optimized with a genetic algorithm.

Table 2. Simulation results UMTS Simulated Values Frequency Band (MHz) 1920-1980 1920-1960 Lockup time <20µs 18.41µs Phase noise <-118 dBc/Hz@1MHz -118 dBc/Hz@1MHz Maximum data rate 2 Mbps 1.3 Mbps Spurs <-110 dBm -109 dBm

3.2. Optimization with Genetic Algorithm

The optimization algorithm we use is based on a genetic algorithm[15] and developed in Visual Basic. The algorithm builds an initial population of possible solutions. It evaluates the performance of each and assigns it a corresponding value referred as fitness. It then selects the better solutions from the population, applies variation operators to them to create a new population for the next generation and iterates.

Figure 5 shows the optimization interface we developed: on the left, the optimization parameters are listed (representing the bandwidth f₀ and the damping factor ξ). On the right, we can see the different genetic algorithm characteristics fixed as following: number of generations: 100, individuals: 10, runs: 1000, selections: 5, mutations: 5.We also defines the range of variation for each parameter of the PLL (I_CP, R, C₁, C₂ and K_VCO)

When applying genetic algorithm, the two key parameters are the number of generations N_G and the population size N_p. If the population is too small, there will not be sufficient diversity in the strings to find the optimal string by a series of operations. If the number of generations is too small, there will not be enough chances to find the optimum. These two parameters are not independent. The larger the population is, the smaller the number of generations needed to have a good chance of finding the optimum is. Moreover, the optimum is not guaranteed; there is just a good chance of finding it.

We optimize the lock time T_r in order to make the PLL faster and then to apply a higher input data rate. Two constraints are introduced: the damping factor ξ and the bandwidth f₀ should be respectively close to 0.707 and 84 kHz. In this case, we can guarantee low spur and low phase noise. We apply the method proposed by Ken Holladay[16]. The different optimization factors (R, C₁, C₂, I_cp and K_vco) are related to T_r and ξ as follows:

(3)

where and l_cp the UMTS canal width.

(4)

where the natural frequency

(5)

where and F_A=1000 KHz.

The obtained optimized solution is shown on Table 3:

Table 3. Optimal solution Factor Low Limit High Limit initial Solution Optimal Solution R (KΩ) 416 1000 416 514 C1 (pF) 1 3 3 1.54 C2 (pF) 10 30 30 15.4 Kvco (MHz/V) 30 100 100 80.5 Icp (µA) 1 1.5 1.5 1.08

The modulator is simulated with the optimal solution. Table 4 details the obtained performances: reduced lock time and spur are obtained (16.39 µs and -115 dBm respectively).

Table 4. Recapitulate table UMTS Initial performances Optimized performances Frequency Band (MHz) 1920-1980 1920-1960 1920- 1980 Lockup time <20µs 18.41µs 16.39µs Phase noise <-118 dBc/Hz@1MHz -118 dBc/Hz@1MHz -118 dBc/Hz Maximum Data rate 2 Mbps 1.3 Mbps 1.8 Mbps Spur <-110 dBm -109 dBm -115 dBm

In general, the lower the loop filter cutoff frequency is, the more the reference leak from the phase comparator is suppressed. As a result, the PLL spur is also suppressed. In addition, a low loop filter cutoff frequency does not suppress phase noise at close-in offset frequencies because the closed loop negative feedback region is narrowed. It makes the PLL response slower and the lock time of frequency switching longer. Conversely, increasing cutoff frequency provides faster PLL response and shorter PLL lock time. While phase noise near the carrier frequency is suppressed, the reference leak is not. It turns out that the PLL output signal is frequency-modulated and contains high level spurs.

Figure 6 shows the simulated phase noise characteristic. We can verify that the phase noise is about -118 dBc/Hz@1MHz.

In addition, with the initial solution, the loop filter cut-off frequency f_C is equal to 127 kHz (computed with CppSim). In this case, we verify that we cannot cover all the frequency band of the UMTS standard (between 1920 MHz and 1980 MHz). After the optimization, f_C has increased all the UMTS frequency band is covered as shown on Figure 7.

Figure 5. PLL optimization interface

Figure 6. Modulator phase noise characteristic

Figure 7. Loop filter output corresponding to the UMTS frequency band

4. High Level Description of the Modulator

CppSim library contains pre-compiled models described in Verilog-A. We used these models to simulate the modulator in Sue2. But when going down in the hierarchical design flow, we should select a transistor level topology for each block constituting the modulator. To reduce the CPU runtime, the modulator is not simulated at the transistor level but each bloc is described in the hardware description language VHDL-AMS.

4.1. Digital Part Modeling

The modulator is simulated in CMOS 350 nm technology. The behaviours of digital building blocks are characterized using delay and slew and included in the behavioural simulation flow. The digital part contains a phase frequency detector (PFD), a Sigma Delta modulator and a N/N+M frequency divider. The reference frequency F_REF is fixed at 26 MHz. To achieve an output frequency varying between 1,92 GHz and 1,98 GHz, the frequency divider ratio should vary between 73.85 and 76.15.

Figure 8. The frequency divider topology

Figure 9. The 2/3 divider bloc topology

Figure 10. The 2/3 divider simulation

The designed frequency divider topology is shown in Figure 8. It uses six 2/3 divider blocs driven by six control blocs. The 2/3 divider topology is detailed on Figure 9. It is composed of two D-latches, OR and AND gates. When the input D_i is low, the CLK frequency is divided by 2. Whereas, when D_i is high, the frequency is firstly divided by 3 then by 2 as shown in Figure 10. We can then verify that the frequency division ratio N varies between 64 and 127, depending on the 6 inputs D_i as[11]:

The PFD topology is depicted on Figure 11. It is mainly composed of D latches. It was described with a VHDL code.

Figure 11. The phase frequency detector topology

The VHDL described Sigma Delta modulator is programmable; it can be a 1^st, 2^nd or 3^rd order as shown in Figure 12. It is composed of three Sigma Delta first-order on cascade. Each one is composed of an ADC converter driven by the output of an integrator that is fed with an input signal summed with the output of a 1-bit DAC fed from the ADC output. It is known that the higher the order of the Sigma Delta modulator, the higher the SNR and then the lower the spur and the phase noise.

Figure 12. Sigma Delta modulator topology

The selection of a channel in the frequency band of the UMTS standard is achieved with a microcontroller. The last permits to drive the Sigma Delta modulator to give an appropriate division ratio. The following figure shows the output signal of the microcontroller for a selected channel frequency f_out equal to 1920 MHz.

Figure 13. Microcontroller output signal

In this case, we have: 73.f_ref< f_out< 74.f_ref. So that:

(6)

with N=2 and M=11.

The microcontroller output signal V_cont is high during 11 clock periods and then low during 2 periods as detailed on Figure 13. When V_cont is high, the divider ratio equals 74, whereas when it is low, the divider ratio equals 73.

All blocs constituting the frequency divider and the ΣΔ modulator are described in VHDL and introduced in Virtuoso Digital implementation software which consists of a capacity-limited version of Encounter RTL Compiler with global synthesis technology. We run the Virtuoso Digital Implementation system to synthesize an RTL netlist. We use the AMS 0.35 µm CMOS technology. Table 5 details the different obtained results. The digital part consumes 6.7 mW, the delay time is around 3.3 µs and the occupied area equals 0.1 mm². We can see in Figure 14 that the frequency divider consumes the higher power and needs the bigger area.

Table 5. Simulation result Digital blocs Cells Leakege(nW) Internal(µW) Net(µW) Power(mW) Delay time (µs) Area(mm2) PFD 12 1.64 382.58 39.41 0.4 0.014 0.0009 Frequency divider 863 87.98 3787.5 2245.45 6.1 3.29 0.1 ΣΔ Modulator 19 3.52 162.22 118.87 0.2 0.012 0.004 Digital part 894 93.14 4332.3 2403.73 6.7 3.3 0.1

Figure 14. Power consumption by a digital part

4.2. Analogue Part Modeling

Figure 15. Charge pump transistor level topology

Figure 16. Output current of the charge pump

The analogue part is composed of a voltage control oscillator, a charge pump and a loop filter. Each block is simulated in CMOS 350 nm technology. The performances selected to build VCO behavioural models are K_VCO, and nonlinearity coefficient A. For the charge pump, we include charge up current I_up and charge down current I_down in the behavioural model. The parameters of the loop filter are the capacitances of C₁ and C₂ together with the resistance of R, which can all be handled directly at system-level simulation. Behaviours of analogue building blocks are mapped into VHDL-AMS models for system-level simulation. We consider PLL system performances as lockup time T_r, power and spur level S_pur.

The design of the charge pump is critical for the achievement of high data rates since it forms the bottleneck in dynamic range that is available to the modulation signal. Figure 15 illustrates the designed topology and Figure 16 shows the simulated output current I_cp. The designed I_up and I_down should be equal for the charge pump, but when the process variations are considered, there is mismatch between I_up and I_down, which introduces extra jitter and impact lock in time significantly. So for the charge pump, we generate transistor level considering average charge current I_cp = 0.5 (I_up + I_down), mismatch current I_mis=abs(I_up − I_down) and transit time. They are introduced in the VHDL-AMS description for the charge pump.

The parameters of loop filters (C₁, C₂ and R) are calculated by Cppsim. The loop filter consists of a passive low pass filter (Figure 17) whose transfer function is expressed as:

(7)

where and with f_Z p

Figure 17. Passive loop filter topology

The VCO transistor level topology is shown on Figure 18 . It consists in an LC oscillator. The simulated output frequency f_out versus the input voltage V_ctrl is depicted on Figure 19. In our case, f_out is modeled by the following second order polynomial[17]:

(8)

f_VCO is the VCO center frequency, K_VCO is its sensitivity and A is a no linearity coefficient; they are extracted from Figure 19 where f_vco is fixed at 1950 MHz.

4.3. Modulator Simulation

In order to validate the ability of VHDL-AMS to successfully describe the modulator performance, a common and complex mixed-signal model has been developed. By using VHDL-AMS, the architecture of each block has been defined and simulated. The CP, the loop filter and the VCO are modeled in VHDL-AMS. The PFD, frequency divider and ∑∆ modulator are lumped into a single model in VHDL. These two parts are simulated under Simplorer 7.0 as illustrated in Figure 20.

Figure 18. VCO transistor level topology

Figure 19. VCO transfert function

We add to the modulator a demodulator based on a PLL to extract the input base band signal. This technique permits to verify that the modulator works well and generates a correct modulated signal. It then permits to compute the maximum input data rate. We can see in Figure 21, that with a data rate equal to 1.8 MHz, we are able to extract the input signal. When increasing this value, a correct extraction becomes not possible. At this step on design, we should do a second optimization to reach the maximum data rate fixed by the UMTS standard (2 Mbit/s).

Figure 20. The modulator simulation in Simplorer environment

Figure 21. Demodulator response

5. Second Step Optimization

With the first optimization using the genetic algorithm, the optimization interface uses an ideal and functional model of the modulator. To find a better solution around the optimized topology, we apply a second optimization step based on experimental designs.

The most frequent designs in optimization problems involving three or more factors are central composite ones, Box-Behnken designs, D-optimal designs, and others, such as Hoke designs[18]. Central composite designs and Box-Behnken designs are the most appropriate to detect curvatures in a multidimensional space, but require a large number of experiments beyond three factors. D-optimal designs are less frequent, but adequate in cases involving linear functions where the factors can only be varied over a restricted area, and thereby creates an irregular experimental domain in which orthogonality cannot be achieved. Hoke designs are economical second-order designs based on irregular fractions of partially balanced type of the 3^k factorial for a number of factors k ≥ 3.

In this work, we consider that the experimental region is a hypercube and we apply a five factor central composite design. Considering that the efficiency of any experimental design is defined as the number of coefficients of the model divided by the number of experiments, central composite design is the most efficient compared to Hoke-D4, Box-Behnken or Doehlert designs. Central composite designs are also more efficient in mapping space: adjoining hexagons can fill a space completely and efficiently, since the hexagons fill space without overlap. The objective of this optimization step is to reduce the PLL lockup time in order to reach an input data rate of 2 Mbps for the designed modulator. The spur level should be maintained as low as possible.

The experimental designs as a function of the selected main factors have to be determined. The lock time and the spur level of the PLL are in trade-off relationship with each other. The analysis of results and the building of experimental designs are carried out with the NEMRODW mathematical statistical software[19].

We apply the experimental design with three levels. In this case, the effect of each factor is studied according to three different values to which we attribute levels +1, 0 and –1 corresponding respectively to the maximum, the middle and the minimum values as illustrated on Table 6.

Table 6. Factor range of variation Variable Factor Level (-1) Level (0) Level (+1) X1 Icp (µA) 1.08 1.08 2.08 X2 R (KΩ) 168 514 460 X3 C1 (pF) 1.04 1.54 2.04 X4 C2 (pF) 10.4 15.4 20.4 X5 Kvco (MHz/V) 63 80.5 98

Table 7. Experiment matrix

To converge to an optimal solution, a relationship between the lock time T_R, spur level S_pur and the five factors X_i is developed. It consists of a full second-order polynomial model obtained by multiple regression technique using Central Composite experimental designs.

Because of the none-linearity of the studied system, the experimental responses Y_i are represented by a quadratic equation of the response surface:

(9)

where b₀ is a constant, b_i, b_ij and b_ii are respectively linear, cross-product and quadratic coefficients.

Y₁ is the response representing the lock time (Y₁ =1/_TR) and Y₂ is the response representing the spur level (Y₂ =1/S_pur);

The Central Composite matrix consists of N experiments with N=f(k), where K is the number of studied variables. In our case K=5 and, therefore, the matrix is comprised of only 27 simulations instead of 3⁵ = 243. For each one, we calculate the lock time T_R and the spur S_pur after simulations in Simplorer 7.0 software. The obtained results are summarized on Table 7.

Coefficients (b_i, b_ii, b_ij) of the postulated model given by expression (9) are calculated on the basis of Central Composite experimental designs with the help of NEMRODW software. The obtained coefficients are summarized on equations (10) and (11).

(10)

(11)

Once coefficients b_i, b_ii and b_ij are determined, we calculate Y₁ and Y₂ using equations (10) and (11). The obtained results are shown on table 8.

The relationship between Y₁, Y₂ and variables may be illustrated graphically by plotting the variation of residus and Y calculated for each response (Figure 22). Such plots are helpful in studying to estimate the quality of the model and validate it. We then compute R² as:

R² = (Sum of squares attributed to the regression)/ Total Sum of squares)

We find R²=0.951 related to Y₁ and R²=0.968 related to Y₂ which reveals that the simulated results fit the second-order polynomial equations (10) and (11). In fact, R² should be greater than 0.8[17].

Figure 22. Residus Variation (a) Y1, b) Y2)

As illustrated on Table 8, the lockup time is reduced (about 14.25 µs). The spur is maintained at a tolerable value (-121 dBm). We can then conclude that the experimental designs help to obtain a faster modulator making possible to apply a higher input signal rate. A 2 Mbps maximum data rate is reached. All the UMTS specifications are satisfied.

Table 8. Comparison of the obtained solutions

6. Modulator Characterization

When increasing the VCO no linearity coefficient A, the lockup time and the spur level increase as shown on Figure 23. To maintain a low lockup time, we need A to be less than 3% whereas to maintain a low spur, A should be less than 1%.

In a second characterization, we can see in Figure 24 the variation of the lockup time and the spur with the dissymmetry coefficient of the charge pump. The design of an efficient modulator needs the current dissymmetry to be less than 35% to have a reduced lockup time and to maintain a low spur level.

Figure 23. Lockup time and Spur level variation with A coefficient

Figure 24. Lockup time and Spur level variation with dissymmetry coefficient

The estimated power consumption of the modulator is about 8.6 mW. The digital part consumes 78% of all the power. The frequency divider and the VCO consume the most power. We have compared the power consumption of our modulator with two other topologies applied for UMTS application. A topology using front-ends empilement consumes 138 mW[26]. A second one using a double IQ consumes 48 mW[26]. Our topology consumes less power because it is based on only one PLL.

Table 9 compares the performances of our modulator with previous works which use a similar topology. The area of silicium is low and the power consumption is relatively reduced. If we simulate the modulator with 65nm technology, the area and the power consumption will be more reuced.

Table 9. Performance comparison

After this characterization, we have to take some constraints into account while passing to the transistor level design. In fact we were able to estimate the power consumption and the silicium area. The charge pump dissymmetry coefficient must be lower than 35% and the no linearity coefficient of the VCO must be lower than 4% to be able to satisfy the UMTS standard.

7. Conclusions

The proposed paper has demonstrated the behavioral modeling and systematic mixed-design of ∑∆ fractional-N PLL acting as a direct modulator using hardware description language VHDL-AMS. The behavioral modeling can provide a fast estimation of PLL performances compared to transistor-level simulation. These HDL behavioral models can be successfully mixed with some circuit blocks (transistor-level) to rapidly evaluate the contribution of each noise source and non-ideal element. This can help designers to test ∑∆ fractional-N PLLs, for a given wireless application, accurately within a minimum CPU time. With the help of an optimization interface based on a genetic algorithm, we can achieve a faster modulator making possible to apply a higher input signal rate and to respect the phase noise limitation of the UMTS standard. A second optimization step based on experimental designs helps to converge to a better optimal solution.

Many computer aided design software are employed to achieve a hierarchical design flow. Our target consists in helping to develop new analogue synthesis techniques to support a future high-level mixed-signal synthesis environment.