Electrical and Electronic Engineering
p-ISSN: 2162-9455 e-ISSN: 2162-8459
2012; 2(2): 68-77
doi: 10.5923/j.eee.20120202.13
Hattab Guesmi 1, 2, Rached Tourki 1
1Electronic and microelectronic laboratory, Monastir university, Monastir, Tunisia
2Faculty of sciences, Jazan university, Jazan, KSA
Correspondence to: Hattab Guesmi , Electronic and microelectronic laboratory, Monastir university, Monastir, Tunisia.
Email: | ![]() |
Copyright © 2012 Scientific & Academic Publishing. All Rights Reserved.
This paper presents a reconfigurable and scalable architecture of a high-performance IP switch to improve network quality of service (QoS). Quality of services, in terms of delay, through-put and loss rate, can be provided by using a mechanism support like scheduling and buffer management architecture of packet switching IP networks. The proposed architecture consists of a new memory management data structure based on circular linked lists. The linked lists include different priorities levels with a pipelined organization for the reconfigurable priority active queues management. The architecture also scales dynamically to support a large number of priority levels and a large queue size. The new data structure enables us to configure the architecture based on network service domain. Detailed description of new data structures of the proposed algorithms and their corresponding implementations are presented as well.
Keywords: Diffserv, IP Switch, Qos, Psoc, CBWFQ, AQM, WFQ, Reconfigurable Architecture, RPAQM
![]() | Figure 1. the output queue manager architecture |
![]() | Figure 2: Stored stamped packets in a sorted manner with CBWFQ algorithm |
![]() | Figure 3. Structure of the priority circular linked list |
![]() | Figure 4. Structure of the queue controller module |
![]() | Figure 5. data structure in IntServ domain |
![]() | Figure 6. data structure in high-speed networks |
![]() | Figure 7. Architecture of the RPAQM in the RTL level |
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