1. Introduction

Starting to attain adequate drive current for the highly scaled MOSFETs (below the 22nm technological node [1]), high transport channel materials (e.g., germanium or III-V thin channels on silicon) may be needed due to a smaller effective mass in Ge can potentially lead to higher carrier mobility and drive currents in Ge MOSFETs than in Si MOSFETs. Ge is particularly well suited for p-type devices, thanks to its high hole mobility which is about four times greater than that of silicon, as well as some processing related issues, such as dopant solubility and Fermi level pinning at the valence band. Ge MOSFETs with different gate dielectrics including HfO₂ [2], ZrO₂ [3], have been demonstrated.

There has been significant effort in simulations to benchmark the performance of nanoscale Ge transistors. Different architectures, substrate orientations and strain effects are investigated by several research groups for Ge NMOS and PMOS. However, replacement of Si channel by Ge requires several critical issues to be addressed in Ge MOS technology. High quality gate dielectric for surface passivation, low parasitic source/drain resistance and performance improvement in Ge NMOS are among the major challenges in realizing Ge CMOS.

In this work we use the nextnano code to simulate a DG-MOSFET with high-k gate dielectric [17] and Ge channel. This simulation tool is based on the self-consistent solution of the Schrödinger, Poisson and current equations [4, 5]. The coupled Poisson-Schrödinger system is solved by an approximate quantum charge density, which is employed inside of Poisson’s equation in order to estimate the dependence of the density on the potential through Schrödinger’s equation. Using this estimator the coupling between both equations is much decreased and rapid convergence is achieved.

The electronic structure is calculated within a single-band or multiband k .p envelope function approximation. The included model for the carrier transport is a Wentzel–Kramer–Brillouin (WKB)- type approach also known as quantum-drift-diffusion (QDD) method, where the carriers are locally in equilibrium, charactized by a local Fermi level [6, 7].

The main aim of this paper is to provide an insight by replacing Silicon in the channel by Ge using different dielectric constants. A comparaison of Ge has been made with both HfO₂, ZrO₂ and Si with SiO₂. Current-voltage (I-V) curves are demonstrated by varying the channel doping concentration.

The outline of the paper is as follows. Section II describes device structure. Section III presents some theoretical aspects. Section IV shows the simulation results using Quantum-drift-diffusion method. Section V concludes the paper.

2. Structure and Simulation Details

Fig. 1 shows the structure of simulated device SOI DGMOSFET. The device parameters is summarised in table 1. This symmetric structure is characterized by p-type doped channel using Si and Ge channel of 6nm width. This channel is embedded between two heavily n-doped source and drain regions of length 10 nm that are connected to source and drain contacts. The junctions are assumed to be abrupt. The polysilicon gates are separated from the Si and the Ge channels by an oxide layer and the power supply voltage V_DD is 0.7V. In order to highlight the performance of device at 22nm technological node and by using different channel doping, we have carried out the calculation by varying different dielectrics ZrO₂ and HfO₂ while maintaining the same channel width (6 nm) and oxide thickness (1.1nm).

Figure 1. Symmetrical DG-MOSFET considered in this work

Table 1. Device parameters taken for design

The channel doping (NA) is changed to maintain the constant Vth which is tabulated in Table 1.

3. Calculation Method

The drift-diffusion model is widely used for simulation of carrier transport in semiconductors this model had been taken for simulating the electronic structure within Nextnano3 [8, 9], and is defined by the basic semiconductor equations. Current density for electrons is given by:

The Poisson equation:

(1)

The current continuity equation for electrons and holes:

(2)

The current relations for electrons and holes:

(3)

The charge density is calculated for a given applied voltage by assuming the carriers to be in a local equilibrium that is characterized by energy-band dependent local quasi-Fermi levels E_Fc(x) for charge carriers of type c (i.e. in the simplest case, one for holes and one for electrons),

(4)

These local quasi-Fermi levels are determined by global current conservation , where the current is assumed to be given by the semi-classical relation :

(5)

The carrier wave functions and energies are calculated by solving the multiband Schrodinger-Poisson equation [4].

The EOT used in this work is that obtained by classical Electrostatic theory in planar devices where:

(6)

The SiO₂, HfO₂ and ZrO₂ permittivities are 3.9,21.2 and 25 respectively.

Due to the increase of the gate dielectric thickness, the leakage current by tunnel effect is then significantly reduced. Indeed, this one decrease exponentially with the gate dielectric thickness

(7)

with:

A: constant m*: carriers effective mass q: electron charge

ħ: Planck constant ФB : unevenness between the level of the Si conduction band and high k material. Loss of voltage through the dielectric.

For long channel devices, the sub-threshold slope, which is the gate voltage excursion required to increase the drain current by one decade in the weak inversion regime, results from the voltage sharing between the gate dielectrics and the depletion region of the transistor. It is expressed as:

(8)

where k is the Boltzmann constant, q the elementary charge, T the temperature, and the depletion and the gate oxide capacitances, respectively.

4. Results

The off-state current is influenced by several parameters such as channel physical dimensions, source/drain junction depth, thickness of gate oxide, channel/surface doping profile and supply voltage (V_dd) [17]. To overcome these impact, we explore the possibility of using Ge as a channel material in p-type MOSFETs with Schottky barrier (SB) contacts. As the Ge concentration is increased, drain current is also increased because of the enhanced mobility.

Fig 2 shows the I_DS versus V_GS curves at constant V_DS of 0.7V for different channel materials for EOT=1.1nm, HfO₂ and ZrO₂ gate dielectrics with Ge shows higher drain current but it requires lower threshold voltage which results short channel effects (SCEs) take dominance, therefore germanium material channel are preferable for given threshold voltage as shown in the inset of Fig 2.

Figure 2. IDS versus VGS characteristics of DGMOSFETs for HfO2and ZrO2

OFF current varies sharply with permittivity with Ge channel. It was revealed that the drain-current for the Ge channel DG MOSFETs was tremendously improved when compared to the Si channel. Also the OFF current for undoped channel raise as the permittivity decrease and its more higher than doped channel.

The off-state current I_off at V_GS=0V When applying HfO₂ is 0.169A/m In the case of ZrO₂ dielectric and Ge channel, the off-state current I_off at V_GS=0V is 0.121A/m. and is 1,09A/m in the case of SiO₂ with Si channel. The HfO₂I_off and ZrO₂ I_off is much less than SiO₂. With increase in channel doping Off-state current get increses. (Table 2).

Table 2. Variation of Ioff with channel doping

The threshold voltage from I_DS–V_GS characteristics at V_DS = 0.7V. is increasing with the increment of permittivity using Ge channel (Fig.3).

Figure 3. Threshold voltage versus Channel doping

The threshold voltage lowering is increasing continuously with the channel Doping Fig.3 shows the variation of threshold with different doping levels [16].

HfO₂ and ZrO₂ gate dielectrics with Ge at 10×10¹⁵ level doping show higher drain current but it require lower threshold voltage thus it is possible to increase subthreshold effects. So we can have desired value of the threshold voltage by varying the channel doping. But high channel doping cannot be done as it leads to gate induced drain leakage. The suitable value of channel doping is 10¹⁵ and value of threshold voltage at this doping level are106.8 mV for the ZrO₂ which is optimum value of threshold voltage for the gate length of 18 nm. Therefore, one using Silicon with SiO₂, it will be higher (Figure 4).

Figure 4. Subthreshold swing versus Channel doping

Table 3. Variation of SS with channel doping

For the various results obtained using simulation approach, lower value of subthreshold swing is desirable so lightly doped channel devices with high permittivity are preferred over doped and undoped channel devices. As we increase the channel doping, subthreshold swing increases linearly as shown in Table 4.

Table 4. Variation of Gm and Gd with channel doping

Figure 5 shows the subthreshold region of MOSFETs which has a significant high gain due to exponential behavior of the drain current thus gives rise to higher transconductance generation factor (Gm/I_D) in the subthreshold regime [10, 11]. gm and Gm/I_D are directly dependent on the drain current. So, the structure having Ge channel gives rise to higher values of transconductance, maximum value of transconductance and maximum value of output conductance are outlined in table4. By comparing these values while dopping channel varying from 0.1×10¹⁵ to 10×10¹⁵ the Tansconductance (G_m) is decreased by 5.4% for SiO₂ and 24.7% for ZrO₂ And 27,9% for HfO₂. G_d is increased by 28.8% for HfO₂ and 10. 3% forZrO₂ and 35.5%f or SiO₂.we can see the variation G_m and G_d in Fig.6 (plots G_m versus channel doping (in the inset Gd versus channel doping)). Higher transconductance means gate has more control over the charge in the channel (Table 4).

Figure 5. Gm/ IDS versus Vg for HfO2and ZrO2 with Ge channel and SiO2 with Si channel

Figure 6. Gm and Gd versus Channel doping

From Fig.5 it’s clear that tas the V_gs increases the G_m / I_d decreases In this figure, the maximum performance can be obtained in ZrO₂ G_m / I_d ratio by comparing with HfO₂ and SiO₂.

ON-State current, decides the driving capability of the device. It is defined as drain to source current when Vgs=V_dd and Vds = V_dd. Fig.7 demonstrates the I_d-V_d characteristics for Si and Ge channel DG MOSFETs. Here, the current in Ge channels is increased compared to Si channel, due to the enhanced mobility. It means the mobility of charge carrier in Ge channel is higher due to which they give higher Ion. saturation occurs around 0.28 volts to 0.41 volts for all the channel materials. Si and SiO₂ gets saturated at almost at the same voltage of 0.28 volts Ge with ZrO₂ and HfO₂ get saturated at 0.41V. have higher saturation current around 935A/m On the whole this figure indicates that Ge using high permittivity have more current density as compared to Si, which is highly desired for channel material.

Figure 7. IDS versus VDS characteristics of DGMOSFETs for HfO2and ZrO2 with Ge channel and SiO2 with Si channel

Table 4 given shows the drive current variation for different doping levels. We can see the decrease of I_ON as channel doping increase. The drain current is dependent on the mobility of carriers which is controlled by the doping concentrations. When the channel doping is kept high which results a lower drain current then the device having higher NA.

Ge MOSFETs with different gate dielectrics including HfO₂ [12, 13], ZrO₂ [13, 14, 15], the high permittivity increases I_on and decrease I_off. More ever the I_on and I_off for HfO₂ and ZrO₂ dielectric are summarized in Tables 2 and 5.

Table 5. Variation of ION with channel doping

The I_on/I_off current ratio represents the power consumption of a device. As we increase the channel doping drive current reduces almost linearly, but off state current decreases exponentially. This leads to increase in I_on/I_off ratio very sharply as shown in Figure 8.

Figure 8. Ratio Ion/Ioffversus channel doping

Figure. 9 shows gate direct tunneling current as function of channel doping for V_DS=V_DD=0.7V, V_GS=0.7V. The gate direct tunneling current takes a minimum value in the case of silicium and maximum value in the case of ZrO₂. So If we increase channel doping and permittivity one parameter get improved while other get worse.

Figure 9. Gate current Igversus channel doping

The improvement in electron density has been investigated in terms of channel doping in Fig.10; this figure shows a slice through the middle of the device (y=T_Si/2=constant) for different channel doping under a drain bias of 0.7V. The electron Density increases and it is highest in the middle of the channel region and is practically zero at the Si/SiO₂; Ge/ZrO₂ and Ge/HfO₂ interfaces. For gate bias voltage equal to 0.7V as shown in the figure of electron density, the Ge channel electron density with HfO₂ and ZrO₂ significantly differs from Si channel using SiO₂ and takes its maximum when reducing the channel doping.

Figure 10. Electron density versus channel doping

5. Conclusions

In comparison to Si as a channel material, Ge is more desirable. Our calculations predict that Ge channel devices Using the high permitivity has a good control of gate and the drain current increases with the increase of permittivity. We also cannot use high doping because mobility degradation of carrier takes place in the channel region. The increase of permitivity with Ge channel when channel doping was raised improve somme parameters like subthreshold swing and highest output conductance at different values of oxide thickness. Our calculated and simulated results show that the optimized value of channel doping is 1×10¹⁵ using ZrO₂.

ACKNOWLEDGEMENTS

The authors would like to thank the support of the Tiziouzou University and also the anonymous reviewers for their critical comments.